Computer systems and electronic devices are continually growing in capability and complexity. The size and complexity of integrated electronic systems are likewise increasing, making it critical that the component parts of these systems operate without fault. This requires that each component, or integrated circuit “chip,” be rigorously tested before it is sold. However, as integrated circuit chips become more powerful, the methods and systems required to detect flaws within them become increasingly sophisticated and expensive.
Integrated circuit designs have become more complex in part because they are made more dense. As a result, they have become progressively harder to test in order to ensure correct and complete functionality. Higher densities are achieved in part by reducing the amount of space between transistors and other components which comprise the integrated circuit. As such, the “place and route” tolerances for the integrated circuit are reduced, and the potential for introducing fabrication errors and introducing structural faults in the circuit increases. Additionally, the complicated placement of the internal structure and nature of the defects encountered in such high density integrated circuits requires the use of sophisticated algorithms in order to ensure adequate defect detection, e.g., being able to determine whether structural defects between the closely spaced gate elements, such as a bit short, broken link, or the like, exist. Hence, the testing cost can be very significant for the latest and largest high density integrated circuits.
Very sophisticated test programs, called automatic test pattern generation (ATPG) programs, are used to analyze the integrated circuit designs and generate therefrom test patterns (e.g., also referred to as test programs or test vectors) used for testing the devices in ATE systems. The objective of the ATPG program is to generate an accurate, high defect coverage test pattern as efficiently as possible, to reduce the cost. As a result of analyzing the target design, the ATPG tool determines a stimulus for all the accessible points of the target design. During chip verification, this stimulus is applied by the tester to the integrated circuit and the real time response of the chip is compared with the pre-computed response of the test pattern.
As discussed above, testing systems, or “testers” are used to apply test vectors to a device under test, capture the test results and shift them out for examination and comparison. However, as with any resource, test facilities have testers of different capabilities and configurations. The testers differ in their clocking characteristics, their power supply capabilities, their memory resources used behind each pin, and most importantly, they different in the number of pins that can supply and receive scan data and functional inputs/outputs, etc. Typically, the more pins available on a tester, the more expensive the tester equipment. For example, today testers cost approximately $5,000.00 per pin supported. The more pins the tester can drive, the more scan chains a design can implement. The more scan chains available, the shorter the scan chains can be, thereby reducing the time it takes to load them up. Conversely, a tester with few pins only supports a design having fewer but longer scan chains. Therefore, testers with high pin count can drive many scan chains and the more scan chains available, the shorter they can be, the faster they load and the more economical the test.
FIG. 1A illustrates an integrated circuit device 18 having fewer external pins, but larger sized scan chains 12a–12d. Scan chains, as are well known, contain scan cells (sequential elements) coupled in series. Because pin count is restricted, only a few scan chains can be accommodated, so they are longer. The reduced number of scan chains require fewer numbers of scan-in pins 14 and scan-out pins 16. Unfortunately, the longer scan chains require more time to scan-in and scan-out their data. This leads to a low performance, low pin count, testing environment. The test vectors developed for this system are also longer and incompatible with high performance testers. ATPG processes that generate long test vectors are used for lower performance testers. FIG. 1D illustrates a low performance, low pin count, tester 40 applied to a device under test 44. The device 44 is placed into a multi-pin socket 46 which connects to the low pin interface 42.
FIG. 1B illustrates an integrated circuit device 26 having many external pins and shorter scan chains 20i. Because the scan chains are shorter, there are many of them and they require high numbers of scan-in pins 22 and scan-out pins 24. The test vectors are also shorter and incompatible with low performance testers. The shorter scan chains 20i require less time to scan-in and scan-out their data and this leads to a high performance, higher pin count, testing environment. This discussion assumes the scan rates are equal. ATPG processes that generate many short test vectors are used for high performance testers. FIG. 1C illustrates a high performance, high pin count, tester 30 applied to a device under test 34. The device 34 is placed into a multi-pin socket 36 which connects to the high pin interface 32.
Although testers vary in pin capacity, nevertheless, the test data generated by ATPG processes is typically generated in an environment that is oblivious to the tester capabilities. For example, in many cases, test patterns tend to be routinely developed for high performance testers without knowing the capabilities of the test facility. This is done because most test engineers are geared to reduce test application time. However, to limit costs, a test facility typically acquires some low cost testers and some high cost testers, which differ in the number of full functional pins they have. If a test facility (e.g., having a mix of both high and low capacity testers) receives test vectors developed for high performance testers, the result will be that many of their low cost testers are left idle because of test vector incompatibility. Having any of these testers idle is a waste of resources and money. It would be advantageous, then, to provide a system that can make full use of the various different types of testers that a facility has but is based on a single set of developed test vectors.